Global Signals - Global Signals - 5.0 English - PG067

Global Slave Interface Clock. For Independent Clock mode, all signals on the AXI Slave interface of an AXI Chip2Chip Master core are synchronous to s_aclk.

For Common Clock mode, all AXI Chip2Chip Master core operations are synchronous to s_aclk.

Physical Interface Clock. The axi_c2c_phy_clk signal is applicable only when Independent Mode operation is selected for the core. AXI Chip2Chip Master core operations excluding the AXI Slave Interface are synchronous to axi_c2c_phy_clk.

SelectIOInterface I/O Reference Clock. This signal is applicable only when the SelectIOinterface is selected as the FPGA interfacing option. The applicable frequency for idelay_ref_clk is 200 MHz or 300 MHz (±10 MHz).

Global Reset. This signal is active-Low and asserted asynchronously. The de-assertion of this signal is synchronized with the clock domain. All applicable clock inputs to the AXI Chip2Chip Master core must be stable when s_aresetn input is deasserted.

Global Master Interface Clock (Independent Clock). The m_aclk signal is an input when the Independent Clock mode of operation is selected for the core.

Note: In Common Clock mode, the m_aclk input has to be connected to m_aclk_out driven by the AXI Chip2Chip Slave core.

Global Master Interface Clock (Common Clock). The m_aclk_out signal is output when the Common Clock Mode of operation is selected for the core.

Global Reset. This signal is active-Low and asserted asynchronously. The de-assertion of this signal is synchronized with the clock domain. All applicable clock inputs to the AXI Chip2Chip Slave core must be stable when m_aresetn input is deasserted.

Master Interface AXI4-Lite Clock. Applicable only when Slave Mode of AXI4-Lite is selected. All signals are sampled on the rising edge of this clock.

Slave Interface AXI4-Lite Clock. Applicable only when Master Mode of AXI4-Lite is selected. All signals are sampled on the rising edge of this clock.