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Supports AXI4 interface data width of 32-bit, 64-bit and 128-bit
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Supports optional AXI4-Lite data width of 32-bit
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Two interface choices:
° Single Ended or Differential SelectIOinterface
° Aurora interface that provides an AXI4-Stream interface to seamlessly integrate into the Aurora IP core
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Independent Master or Slave mode selection for AXI4 and AXI4-Lite interfaces
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Supports Common Clock or Independent Clock operations
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Supports multiple Width Conversion options for reduced I/O utilization
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Supports Link Detect FSM with deskew operation for the SelectIOinterface
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Supports Link Detect FSM and implements Hamming SECDED error correction code (ECC) for Aurora interfaces
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Allows all five AXI4 channels to operate independently
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Supports an additional high-priority cut through channel for communicating interrupts
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Supports completion of the pending AXI transactions in case the link fails between chip2chip master and chip2chip slave
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Provides a dedicated high-priority internal channel for link status monitoring and reporting