Device Interface Signals - Device Interface Signals - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

The following table describes the Master Device Interface signals for the AXI Chip2Chip core.

Table 1. Device Interface Signals
Name Direction Description
Single Ended SelectIO Interface
axi_c2c_selio_tx_clk_out Output SelectIOFPGA interface clock from Master device to Slave device.
axi_c2c_selio_tx_data_out[m–1:0] Output SelectIOFPGA Interface Data from Master device to Slave device. ‘m’ is the number of Output I/Os required for Master-to-Slave device interfacing. For details, see User Tab.
axi_c2c_selio_rx_clk_in Input SelectIOFPGA interface clock from Slave device to Master device.
axi_c2c_selio_rx_data_in[m–1:0] Input SelectIOFPGA interface signals from Slave device to Master device. ‘m’ is number of Input I/Os required for Slave to Master device interfacing. For details, see User Tab.
Differential SelectIO Interface

axi_c2c_selio_tx_diff_clk_out_p

axi_c2c_selio_tx_diff_clk_out_n

 Output SelectIOdifferential clock from Master to Slave device. Differential clocking is valid when C_USE_DIFF_CLK is set to 1.

axi_c2c_selio_tx_diff_data_out_p[m–1:0]

axi_c2c_selio_tx_diff_data_out_n[m–1:0]

 Output

SelectIOdifferential Data from Master to Slave device. m is the number of Output I/Os required for Master-to-Slave device interfacing. For details, see Chip2Chip PHY Width in Chapter 4.

Differential data is valid when C_USE_DIFF_IO is set to 1.

axi_c2c_selio_rx_diff_clk_in_p

axi_c2c_selio_rx_diff_clk_in_n

 Input SelectIOdifferential clock from Slave to Master device. Differential clocking is valid when C_USE_DIFF_CLK is set to 1.

axi_c2c_selio_rx_diff_data_in_p[m–1:0]

axi_c2c_selio_rx_diff_data_in_n[m–1:0]

 Input SelectIOdifferential data signals from Slave to Master device. m is number of Input I/Os required for Slave to Master device interfacing. For details, see User Tab. Differential data is valid when C_USE_DIFF_IO is set to 1.
aurora_do_cc Output Clock compensation pattern generator signal used by aurora core. Asserted for every 10 μ s intervals. This port is removed in aurora6466 b_v10_0.This can be left open.
aurora_pma_init_in Input PMA initialization signal. Input signal that initializes the serial transceiver cells.
aurora_pma_init_out Output PMA initialization signal to Aurora IP. This signal is generated from the aurora_pma_init_in signal.
aurora_init_clk 1 Input Single-ended init_clk_out signal from the Aurora IP.
aurora_mmcm_not_locked Input MMCM locked indication from the Aurora IP. This signal indicates that the user clock from the Aurora IP is not stable.
aurora_reset_pb Output Reset signal for the Aurora block. This signal should be connected to the reset_pb signal of the Aurora IP.
  1. For UltraScale and UltraScale+ devices, this clock should be the same as init clock input for Aurora. For more details, see Aurora 8B/10B LogiCORE IP Product Guide (PG046) and Aurora 64B/66B LogiCORE IP Product Guide (PG074).