Core-Specific Checks - Core-Specific Checks - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English
The following checks can further the debugging process:
  • Check that the axi_c2c_multi_bit_error_out signals of both the Master and Slave cores are not asserted. The axi_c2c_link_status_out signal should be asserted High after the cores are calibrated.
  • If the Slave is reset during normal operation (axi_c2c_link_error_out), reset the entire Master-Slave system.
  • After downloading the software in any of the boards, reset the entire system. If there is no reset propagation, the Slave needs to be reset first, followed by the Master.