The following figure provides the clocking requirement for the SelectIO interface. In addition to AXI clocks, the deskew function, when enabled, requires an additional 200 MHz or 300 MHz (± 10 MHz) reference clock. Both AXI Chip2Chip Master and AXI Chip2Chip Slave cores can be independently selected for either Common Clock or Independent Clock operations. When the AXI Chip2Chip Slave core is selected for Common Clock operation, the core provides clock and reset (Link Status) to the interfacing slave AXI system.
When the AXI4-Lite interface is enabled, it
always operates on an independent axi_lite clock input. The
AXI4-Lite Master core operations are synchronous to s_axi_lite_aclk, and the AXI4-Lite
Slave core operations are synchronous to m_axi_lite_aclk.
The following figure shows the clocking, reset and interface connectivity
with the Aurora IP core. In this example, the Aurora core requires differential GT reference
clock (gt_refclk) inputs and differential free running clock
(init_clk) inputs for core operations. The Aurora core
provides the single-ended PHY clock (user_clk) and single
ended aurora_init_clk to the AXI Chip2Chip
core.
The stability of user_clk is validated by
mmcm_not_locked output from the Aurora core. AXI Chip2Chip link-up operations are initiated only when Aurora output mmcm_not_locked is deasserted and channel_up is asserted. On link-up, the AXI Chip2Chip generates a
pulse (stay alive pulse) on do_cc output once in every 10,000
clock cycles of free running aurora_init_clk.
The AXI Chip2Chip Master core with Aurora interface supports
only independent clock mode. The AXI Chip2Chip Slave core supports both Common
Clock and Independent clock modes. The s_aclk is always
required as AXI input clocks for AXI Chip2Chip Master core. The m_aclk is always required as AXI input clocks for the AXI Chip2Chip Slave core. The m_aclk_out is
provided as an additional clock output in Common Clock mode. The m_aclk_out output can be used as an AXI System Clock. In addition, it should be
connected to m_aclk input of the AXI Chip2Chip
Slave core.
In common clock operations, the AXI Chip2Chip Slave core
connects the Aurora user_clk to the m_aclk_out output of the core. In this case, the pma_init reset must be handled externally, and asserting pma_init resets the MMCM generating the user_clk.
It is also recommended to connect pma_init to the m_aresetn input of the AXI Chip2Chip Slave core in
Common Clock mode.