Figure 1.
Vivado IDE for Advanced AXI
Chip2Chip Core Parameters
The preceding figure shows the Vivado IDE for advanced AXI Chip2Chip core parameters. This tab includes the following options for the SelectIOFPGA interface:
- Enable Differential Clock
- When set to 1, implements differential I/O buffer on the two clocks I/Os used for device interfacing. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.
- Enable Differential IO Data
- When set to 1, implements differential I/O buffer on the data I/Os used for device interfacing. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.
- Enable Narrow Burst Property
- Setting simply sets the Narrow Bus attribute on the AXI4 bus interface. This does not affect the IP operation.