AXI Interface Signals - AXI Interface Signals - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID: PG067
Release Date: 2026-02-11
Version: 5.0 English

The following table describes the AXI Interface signals for the AXI Chip2Chip core.

Table 1. AXI Interface Signals
Name	Direction	Description
s_axi_*	NA	AXI4 Slave Interface Signals. These signals are available only in master mode. See the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4 Slave signals.
m_axi_*	NA	AXI4 Master Interface Signals. These signals are available only in slave mode. See the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI Master signals.
s_axi_lite_*	NA	AXI4-Lite Slave Interface Signals. These signals are available only when AXI4-Lite mode is set as Master. See the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI4 Slave signals.
m_axi_lite_*	NA	AXI4-Lite Master Interface Signals. These signals are available only when AXI4-Lite mode is set as Slave. See the Vivado Design Suite: AXI Reference Guide (UG1037) for AXI Master signals.