Width Conversion - 2.1 English - PG059

Each of the SI and MI on the AXI Interconnect core can be individually configured to have a data width of 32, 64, 128, 256, 512, or 1024 bits. When the data width of an interface is configured differently than the data width of the internal Crossbar, a width conversion module is automatically instantiated along the pathway.

The width conversion functions differ depending on whether the datapath width gets wider (upsizing) or narrower (downsizing) when moving in the direction from the SI toward the MI. The width conversion functions are the same in either the SI hemisphere (translating from an SI to the Crossbar) or the MI hemisphere (translating from the Crossbar to a MI).

Selecting a sufficiently high-data width for the AXI Crossbar can avoid loss of data bandwidth. For example, you could elect to set the AXI Crossbar to match the width of a speed-critical slave, such as a memory controller, even though all the masters that access that slave have narrower data widths.

With that setting, the AXI Interconnect core can perform data packing (Write transactions) or serialization (Read transactions) concurrently along multiple SI slot pathways in the SI hemisphere while the wide slave device and crossbar periodically maintain a data throughput rate higher than any one master device can sustain.

In contrast, selecting a lower data width for the AXI Crossbar can reduce logic resource utilization for less speed-critical designs. When seeking to minimize resource utilization, set the data width of the AXI Crossbar so that it minimizes the total number of width converters.

The following table lists the transformations performed by the Data Width Converter for various parametric configurations and incident SI transactions. Table 2 provides details of the resulting output (MI-side) transactions for each of the transformations. Use the Transformation Formula name in Table 1 as an index into Table 2.

The following tables use these following designators when describing properties, signals, and derived equations.

1. si.DW = SI_DATA_WIDTH
2. mi.DW = MI_DATA_WIDTH
3. si.LEN = S_AXI_AWLEN or C_S_AXI_ARLEN, as applicable
4. si.ADDR = S_AXI_AWADDR or C_S_AXI_ARADDR, as applicable
5. si.Bytes = si.DW / 8
6. mi.Bytes = mi.DW / 8
7. mi.ByteMask = mi.Bytes – 1
8. si.SIZE = S_AXI_AWSIZE or S_AXI_ARSIZE, as applicable
9. si.SizeMask = (2**si.SIZE) – 1
10. mi.SizeMask = (2**mi.SIZE) – 1
11. mi.AlignedStart = si.ADDR & ~mi.ByteMask
12. mi.AlignedEnd = ((si.ADDR & ~si.SizeMask) + (si.LEN * 2**si.SIZE)) & ~mi.ByteMask
13. mi.upsize_LEN = (mi.AlignedEnd - mi.AlignedStart) / mi.Bytes
14. si.conv_ratio = ceil((2**si.SIZE) / mi.Bytes)
15. si.downsize_LEN = (si.LEN+1) * si.conv_ratio - 1
16. mi.AlignedAdjustment = (si.ADDR & si.SizeMask & ~mi.ByteMask) / mi.Bytes
17. si.burst_bytes = 2**si.SIZE * (si.LEN+1)
18. si.burst_mask = si.burst_bytes - 1
19. si.wrap_address = si.ADDR & ~si.burst_mask
20. si.wrap1_LEN = (si.burst_bytes - (si.ADDR & si.burst_mask)) / mi.Bytes - 1
21. si.wrap2_LEN = (si.ADDR & si.burst_mask) / mi.Bytes - 1
22. Downsize_ratio = ceil((2**si.SIZE) / (MI_DATA_WIDTH / 8))
23. MI beats = SI beats * Downsize_ratio (less MI beats skipped due to unaligned ADDR)
24. max_beats = 256 if (PROTOCOL == AXI4), 16 if (PROTOCOL == AXI3)