The AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. Each connected master could be a core that originates AXI transactions (endpoint master) or a master interface of an upstream AXI Interconnect core being cascaded. Each connected slave could be the final target of AXI transactions (endpoint slave) or a slave interface of a downstream AXI Interconnect core being cascaded. A connected master or slave could also be any of the AXI Infrastructure conversion/storage cores, although these functions are typically performed inside the AXI Interconnect core to avoid clutter in the top-level design.
Each AXI Interconnect core can be configured to perform one the following general connectivity patterns:
•N-to-M Interconnect (Crossbar Mode)
•N-to-M Interconnect (Shared Access Mode)
The Interconnect can also be configured to connect one master to one slave, in which case the IP integrator will automate the instantiation and configuration of any couplers that are needed along the pathway.