Each of the SI, MI, and Crossbar aclk is accompanied by an aresetn
input, which must be synchronized to the corresponding aclk .
(This version of the AXI Interconnect core does not internally resynchronize any aresetn inputs.)
All AXI Interconnect
Infrastructure cores deassert all valid
and ready outputs shortly after aresetn is sampled active, and for the
duration of the aresetn pulse.
Important: Each of the SI and MI must be put
into the reset state at some time during the reset cycle of the Crossbar, and vice-versa, for
every occurrence of reset. None of the AXI Interconnect cores support partial resetting. That
is, whenever one interface is reset, all interfaces must be reset, and the resets must
overlap. It is not necessary for multiple
aresetn inputs to
be deasserted during the same clock cycle.Important: All cores connected to the AXI Interconnect core,
or to any AXI Infrastructure core described in this document, must have their connected AXI
interface put into the reset state (
aresetn outputs
deasserted) at some time during the reset cycle of the AXI Interconnect core (must overlap),
for every occurrence of reset. None of the AXI Interconnect cores support resetting one end of
an AXI interface connection without the other, in either direction. It is not necessary for
the aresetn input of the connected core to be
deasserted during the same clock cycle as the AXI Interconnect core. Recommended: As a general design guideline,
AMD recommends asserting system
aresetn signals for a minimum of 16 clock cycles (of the slowest aresetn ), as that is known to satisfy the preceding reset
requirements.