Master I/O Signals - 2.1 English - PG059

m_axi_awid

Output

M*ID_WIDTH

Write Address Channel Transaction ID.

m_axi_awaddr

Output

M*ADDR_WIDTH

Write Address Channel Address.

m_axi_awlen

Output

AXI4: M*8

AXI3: M*4

Write Address Channel Burst Length code. (0–255).

m_axi_awsize

Output

M*3

Write Address Channel Transfer Size code (0–7).

m_axi_awburst

Output

M*2

Write Address Channel Burst Type (0–2).

m_axi_awlock

Output

AXI4: M*1

AXI3: M*2

Write Address Channel Atomic Access Type
(0, 1).

m_axi_awcache

Output

M*4

Write Address Channel Cache Characteristics.

m_axi_awprot

Output

M*3

Write Address Channel Protection Bits

m_axi_awregion

Output

M*4

AXI4 Write Address Channel address region index.

m_axi_awqos⁽¹⁾

Output

M*4

Write Address Channel Quality of Service.

m_axi_awuser

Output

M*AWUSER_WIDTH

User-defined AW Channel signals.

m_axi_awvalid

Output

M*1

Write Address Channel Valid.

m_axi_awready

Input

REQ

M*1

Write Address Channel Ready.

m_axi_wid

Output

M*ID_WIDTH

Write Data Channel Transaction ID for AXI3 slaves.

m_axi_wdata

Output

M*DATA_WIDTH

Write Data Channel Data.

m_axi_wstrb

Output

M*DATA_WIDTH/8

Write Data Channel Data Byte Strobes.

m_axi_wlast

Output

1

Write Data Channel Last Data Beat.

m_axi_wuser

Output

M*WUSER_WIDTH

User-defined W Channel signals.

m_axi_wvalid

Output

M*1

Write Data Channel Valid.

m_axi_wready

Input

REQ

M*1

Write Data Channel Ready.

m_axi_bid

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

M*ID_WIDTH

Write Response Channel Transaction ID.

m_axi_bresp

Input

0b00

M*2

Write Response Channel Response Code (0–3).

m_axi_buser

Input

AXI3, AXI4: 0

AXI4-Lite: d/c

M*BUSER_WIDTH

User-defined B Channel signals.

m_axi_bvalid

Input

REQ

M*1

Write Response Channel Valid.

m_axi_bready

Output

M*1

Write Response Channel Ready.

m_axi_arid

Output

M*ID_WIDTH

Read Address Channel Transaction ID.

m_axi_araddr

Output

M*ADDR_WIDTH

Read Address Channel Address.

m_axi_arlen

Output

AXI4: M*8

AXI3: M*4

Read Address Channel Burst Length code (0–255).

m_axi_arsize

Output

M*3

Read Address Channel Transfer Size code (0–7).

m_axi_arburst

Output

M*2

Read Address Channel Burst Type (0–2).

m_axi_arlock

Output

AXI4: M*1

AXI3: M*2

Read Address Channel Atomic Access Type (0,1).

m_axi_arcache

Output

M*4

Read Address Channel Cache Characteristics.

m_axi_arprot

Output

M*3

Read Address Channel Protection Bits.

m_axi_arregion

Output

M*4

AXI4 Read Address Channel address region index.

m_axi_arqos⁽¹⁾

Output

M*4

AXI4 Read Address Channel Quality of Service.

m_axi_aruser

Output

M*ARUSER_WIDTH

User-defined AR Channel signals.

m_axi_arvalid

Output

M*1

Read Address Channel Valid.

m_axi_arready

Input

REQ

M*1

Read Address Channel Ready.

m_axi_rid

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

M*ID_WIDTH

Read Data Channel Transaction ID.

m_axi_rdata

Input

REQ

M*DATA_WIDTH

Read Data Channel Data.

m_axi_rresp

Input

0b00

M*2

Read Data Channel Response Code (0–3).

m_axi_rlast

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

M*1

Read Data Channel Last Data Beat.

m_axi_ruser

Input

AXI3, AXI4: 0

AXI4-Lite: d/c

M*RUSER_WIDTH

User-defined R Channel signals.

m_axi_rvalid

Input

REQ

M*1

Read Data Channel Valid.

m_axi_rready

Output

M*1

Read Data Channel Ready.

Notes:

1.Although the QOS signals are defined only by the AXI4 protocol specification, this interconnect IP core also propagates QOS signals for any MI slot configured as AXI3.

Port Signal Name

Direction

Default

Width

Description (Range)

aclk

Input

REQ

1

clock input.

aresetn

Input

REQ

1

Global Reset (active-Low).