| Core
Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
, AMD UltraScale™
, 7 series FPGAs,
AMD Zynq™ 7000
|
| Supported User Interfaces |
AXI4, AXI4-Lite, AXI3
|
| Resources |
See Table 2 through Table 1. |
| Provided with Core |
| Design Files |
Verilog and VHDL |
| Example Design |
Not Provided |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver
2
|
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 54453
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the Vivado IP catalog. Support for the AXI
Interconnect IP is not migrated beyond the AMD
UltraScale+ family. AXI switching for
the AMD
Versal family and beyond should instead use the AXI Smartconnect
IP, which provides compatible functionality. For more information, see
SmartConnect
LogiCORE IP Product Guide (PG247). Also, support does not
extend beyond the AMD UltraScale+™
family for any the AXI infrastructure cores covered
in this Product Guide, except AXI Register Slice.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- The Xilinx LogiCORE AXI Interconnect IP will be deprecated in a
future Vivado Design Suite release. To ensure long-term support and
access to the latest features, you are strongly encouraged to migrate to the
recommended replacement IP cores:
- For IP integrator (IP integrator)–based designs, migrate from AXI
Interconnect v2.1 to SmartConnect v1.0.
- For RTL-based designs, migrate from AXI Interconnect v1.7 to AXI Switch
v1.0.
|