The AXI Interconnect core is comprised of multiple LogiCORE IP instances (infrastructure cores). Each of the AXI4 memory-mapped infrastructure cores that comprise the AXI Interconnect core are fully described in this document. The following features apply to the AXI Interconnect core in general and to all infrastructure cores described in this document unless otherwise noted:
- AXI protocol compliant. Can be configured to support AXI3, AXI4, and AXI4-Lite protocols.
- Interface data widths:
- AXI4 and AXI3: 32, 64, 128, 256, 512, or 1,024 bits
- AXI4-Lite: 32 or 64 bits
- Address width: Up to 64 bits
- USER width (per channel): Up to 1,024 bits
- ID width: Up to 32 bits
- Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization.