Common Configuration - Common Configuration - 2.1 English - PG059

• Connectivity Mode: SAMD (Maximize Performance strategy)
• Protocol: AXI4 or AXI3
• Data Width: 64 (Data width derating factors shown in table.)
• Read/Write Connectivity: all MI fully connected (Read-only and write-only derating factors shown in table.)
• Thread ID Width: 2 (all SI)
• Address Width: Global = 32; per MI = 16 (1 address range)
• Read/write Acceptance: 4
• Read/write Issuing: 8
• Arbitration Priority: 0 (round-robin)
• Single Thread: Disabled
• User Width: 0
• Target device: xc7vx485t

LUTs

Slice LUTs utilization for 64-bit Data Width

FFs

Slice Flip-Flops utilization for 64-bit Data Width

base_LUTs

Baseline LUTs, independent of data width

base_FFs

Baseline FFs, independent of data width

LUTs_per_bit

LUTs_for_width_DW = base_LUTs + (DW * LUTs_per_bit)

FFs_per_bit

FFs_for_width_DW = base_FFs + (DW * FFs_per_bit)

RO_LUTs, RO_FFs

All SI and MI Read-Only (64-bit data width)

WO_LUTs, WO_FFs

All SI and MI Write-Only (64-bit data width)

Utilization (LUTs) for crossbar with RW_SI and RW_MI read/write slots, RO_SI, and RO_MI read-only slots and WO_SI and WO_MI write-only slots (64-bit data width) is approximately (LUTs[(RW_SI + RO_SI), (RW_MI + RO_MI)] * RO_LUTs%) + (LUTs[(RW_SI + WO_SI), (RW_MI + WO_MI)] * WO_LUTs%); similarly for FFs. (SAMD Crossbar shares no resources between read and write pathways; thus RO% + WO% always = 100%.)