Common Configuration - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)
Document ID
PG059
Release Date
2025-12-19
Version
2.1 English
  • ID Width: 2 (AXI4 and AXI3 only)
  • Read/Write Mode: Read/Write
  • Address Width: 22
  • User Width: 0
  • Target device: xc7vx485t

Utilization is shown for each AXI channel. Total utilization is the sum of all enabled channels based on their Register Slice Option settings. (BYPASS uses no resources.)

Table 1. AXI Register Slice Resource Utilization
Protocol AXI Channel Data Width FULL LIGHT
LUTs FFs LUTs FFs

AXI4 or

AXI3

R 32 50 80 10 40
64 80 140 10 70
128 140 270 10 140
256 270 530 10 270
512 530 1040 10 520
1024 1040 2060 10 1030
W 32 50 80 10 40
64 80 150 10 80
128 150 300 10 150
256 300 580 10 290
512 590 1160 10 580
1024 1160 2310 10 1160
AR N/A 60 110 10 60
AW N/A 60 110 10 60
B N/A 10 10 10 10
AXI4-Lite R 32     10 40
64     10 70
W 32     10 40
64     10 80
AR N/A     10 30
AW N/A     10 30
B N/A     10 10