Asynchronous Clock-Domain-Crossing Constraints - 2.1 English - PG059

The AXI Clock Converter IP core and the AXI Data Width Converter IP core generate IP-level XDC constraint files, whether they are used stand-alone or as part of an AXI Interconnect core. When either is configured to perform asynchronous clock-domain-crossing, the generated XDC file contains set_max_delay constraints to prevent the resynchronized pathways from causing timing violations during static timing analysis. Otherwise, the XDC file is empty. If generated, the constraints use the periods of the connected clocks, defined at the system level, to derive their delay values. In order for these IP-level constraints to work properly, the following rules apply to your system-level timing constraints whenever the IP core performs asynchronous clock conversion:

1. Each of the nets connected to the s_axi_aclk and m_axi_aclk ports of the IP core must have exactly one clock defined on it, using either
   1. a create_clock command on a top-level clock pin specified in your system XDC file, or
   2. a create_generated_clock command, typically generated automatically by an IP core producing a derived clock signal, such as clk_wiz .
2. The s_axi_aclk and m_axi_aclk ports of the IP core should not be connected to the same clock source.

For more details about synthesis and implementation, see in the Vivado Design Suite User Guide: Designing with IP (UG896).