In the CORE Generator tool, AXI Interconnect v1.x core supported only N:1 connectivity and therefore assumed the M00_AXI interface was mapped to the entire address space, as defined by the ADDR_WIDTH parameter. The corresponding parameter settings in AXI Interconnect v2.0 core are:
•M00_A00_BASE_ADDR = 0
•M00_A00_ADDR_WIDTH = ADDR_WIDTH