Introduction
Features
IP Facts
Overview
AXI Infrastructure Cores
Feature Summary
AXI Crossbar
AXI Data Width Converter
AXI Clock Converter
AXI Protocol Converter
AXI Register Slice
AXI Data FIFO
AXI MMU
Applications
AXI Interconnect Core Limitations
Licensing and Ordering
Product Specification
Use Models
N-to-1 Interconnect
1-to-N Interconnect
N-to-M Interconnect (Crossbar Mode)
N-to-M Interconnect (Shared Access Mode)
Standards
Latency
AXI Crossbar
AXI Register Slice
AXI Data FIFO
AXI Clock Converter
AXI Data Width Converter
AXI Protocol Converter
AXI MMU
Maximum Performance
AXI Crossbar Performance: SAMD, AXI4 Protocol
AXI Crossbar Performance: SASD, AXI4 Protocol
AXI Crossbar Performance: SASD, AXI4-Lite Protocol
AXI Clock Converter
AXI Data FIFO
AXI Data Width Converter
AXI MMU
AXI Protocol Converter
AXI Register Slice
Resource Utilization
AXI Crossbar Resource Utilization: SAMD, AXI4 Protocol
Common Configuration
AXI Crossbar Resource Utilization: SASD, AXI4 Protocol
Common Configuration
AXI Crossbar Resource Utilization: SASD, AXI4-Lite Protocol
Common Configuration
AXI Clock Converter Resource Utilization
Common Configuration
AXI Data FIFO Resource Utilization
Common Configuration
AXI Data Width Converter Resource Utilization: AXI4 Upsizer
Common Configuration
AXI Data Width Converter Resource Utilization: AXI4 Downsizer
Common Configuration
AXI Data Width Converter Resource Utilization: AXI4-Lite
Common Configuration
AXI MMU
Common Configuration
AXI Protocol Converter Resource Utilization
Common Configuration
AXI Register Slice Resource Utilization
Common Configuration
Port Descriptions
AXI Interconnect Core I/O Signals
Slave Interface I/O Signals
Master Interface I/O Signals
AXI Crossbar Core I/O Signals
Slave I/O Signals
Master I/O Signals
Other AXI Infrastructure Core I/O Signals
Slave I/O Signals
Master I/O Signals
Register Space
Designing with the Core
AXI Interconnect Core Functionality
AXI Crossbar Functionality
Crossbar Signal Interface
Use of ID Signals
Address Decode
Transaction Acceptance and Issuing Limits
Transaction Arbitration
Cyclic Dependency Avoidance
How Deadlock Occurs
Avoiding Deadlock Using Single Slave Per ID
Error Signaling
Width Conversion
AXI Downsizer
AXI Upsizer
Clock Conversion
Protocol Conversion
Conversion to AXI4-Lite
AXI4-to-AXI3 Converter
Other Conversions
AXI Register Slices
AXI Data FIFO
AXI MMU
Design Parameters
AXI Interconnect Core Parameters
AXI Crossbar Core Parameters
Other AXI Infrastructure Core Parameters
AXI Data Width Converter Parameters
AXI Clock Converter Parameters
AXI Protocol Converter Parameters
AXI Data FIFO Parameters
AXI Register Slice Parameters
AXI MMU Parameters
Clocking
Resets
Design Flow Steps
Customizing and Generating the Core
AXI Interconnect Core — Top Level Settings
Interconnect Optimization Strategy
Number of Slave Interfaces
Number of Master Interfaces
AXI Interconnect Core — Slave Interfaces Tab
Enable Register Slice
Enable Data FIFO
AXI Interconnect Core — Master Interfaces Tab
Enable Register Slice
Enable Data FIFO
AXI Interconnect Core — Advanced Options Tab
Clock Domain Crossing MTBF Options
Interconnect Crossbar Options
Interconnect Debug Options
Master Interface Options
Slave Interface Options
AXI Crossbar Core — Global Tab
Number of Slave Interfaces
Number of Master Interfaces
Crossbar Optimization Strategy
PROTOCOL
Address Width
Data Width
ID Width
User Signal Widths
Crossbar Options
AXI Crossbar Core — Slave Interface Tab
Arbitration Priority
Read Acceptance
Write Acceptance
Thread ID Width
Single Thread
AXI Crossbar Core — Master Interface Tab
Read Issuing
Write Issuing
Secure Slave
AXI Crossbar Core — Address Tab
Number of Address Ranges
Base Addr
Address Width
AXI Crossbar Core — Connectivity Tab
Connectivity
AXI Data Width Converter
Protocol
READ_WRITE Mode
Address Width
SI Data Width
MI Data Width
SI ID Width
FIFO_MODE
ACLK_RATIO
ACLK_ASYNC
Synchronization Stages
AXI Clock Converter
Protocol
READ_WRITE Mode
Address Width
Data Width
ID Width
User signal widths
Clock Conversion Options
Synchronization Stages
AXI Protocol Converter
SI Protocol
MI Protocol
READ_WRITE Mode
Address Width
Data Width
ID Width
Protocol CONVERSION Options
AXI Data FIFO Core
PROTOCOL
READ_WRITE Mode
Address Width
Data Width
ID Width
User Signal Widths
Write FIFO Options
Read FIFO Options
AXI Register Slice Core Settings Tab
PROTOCOL
READ_WRITE Mode
Address Width
Data Width
ID Width
User Signal Widths
Register Slice Options
AXI MMU – Settings Tab
PROTOCOL
READ_WRITE Mode
SI Address Width
MI Address Width
Data Width
ID Width
User Signal Widths
AXI MMU – Address Tab
Number of Address Ranges
Base Addr
Addr Width
READ/WRITE Access
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Asynchronous Clock-Domain-Crossing Constraints
Timing Closure of AXI Memory-Mapped Connections Across SLRs in SSI Devices
Example Design
Upgrading
Migration from CORE Generator System AXI Interconnect v1.x Core
Address Range
Migration from XPS AXI Interconnect v1.x Core
Address Range
Range Check
Upgrading in the Vivado Design Suite
Parameter Changes
Protocol Converter Core
Port Changes
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the AXI Interconnect Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Vivado Design Suite Debug Feature
Interface Debug
Debugging Guidance for AXI Interconnect Cores in the IP Integrator
Definitions, Acronyms, and Abbreviations
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices
FULLY_REGISTERED
Register slices (each applicable channel): One latency cycle with no
bubble cycles (best-case 100% channel bandwidth).
LIGHT_WEIGHT
Register slices (each applicable channel): One latency cycle with one
bubble cycle (best-case 50% channel bandwidth), which is appropriate for AW, AR, and B
channel transfers, and all transfers involving AXI4-Lite
endpoints.
SI Reg or MI Reg
One latency cycle, no bubble cycles.
SLR Crossing mode and SLR TDM Crossing mode
Three latency cycles (of aclk), no bubble cycles.
Multi SLR Crossing
Overall latency varies between 1 and 17 cycles depending on the number of SLR
boundaries crossed and the number of pipeline stages configured within each SLR
region.