AXI Register Slice - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

Individually configurable for each of the 5 AXI channels.

Facilitates timing closure by trading-off frequency versus latency.

One latency cycle per register-slice by default.

Able to propagate AXI traffic with no loss in data throughput (without bubble cycles) under all AXI handshake conditions.

Optional pipelining to cross SLRs in SSI devices.