•FULLY_REGISTERED: register slices (each applicable channel): 1 latency cycle with no bubble cycles (best-case 100% channel bandwidth).
•LIGHT_WEIGHT: register slices (each applicable channel): 1 latency cycle with one bubble cycle (best-case 50% channel bandwidth), which is appropriate for AW, AR, and B channel transfers, and all transfers involving AXI4-Lite endpoints.
•SI Reg or MI Reg: One latency cycle, no bubble cycles.
•SLR Crossing mode and SLR TDM Crossing mode: 3 latency cycles (of aclk), no bubble cycles.
•Multi SLR Crossing: Overall latency varies between 1 and 17 cycles depending on the number of SLR boundaries crossed and the number of pipeline stages configured within each SLR region.