AXI MMU - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

Common Configuration:

Protocol: AXI4, AXI3 or AXI4-Lite

Data Width: 32-1024

Address Width = 32

Number of address ranges: 32

Note:   The specifications in these tables are derived by implementing the configured IP in isolation, characterizing clock frequency based on static timing results, and then applying a 10% guardband below the highest constrained clock frequency that meets timing.

Table 2-13:      AXI MMU Performance

Performance (MHz)

Virtex-7 and Kintex-7 (and its Zynq-7000 derivatives), Speed Grade -2

Kintex UltraScale,
Speed Grade -2

Artix-7 (and its Zynq-7000 derivatives), Speed Grade -2

350

400

305