AXI Interconnect Core Parameters - 2.1 English

AXI Interconnect Core Parameters - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID

PG059

Release Date

2025-12-19

Version

2.1 English

Table 1, Table 2, and Table 4 list the parameters used to configure the AXI Interconnect core only. When deploying the AXI Interconnect core in your design, additional parameters belonging to each of the underlying AXI Infrastructure cores are also available for customization when not automatically set according to system connectivity.

Table 1. AXI Interconnect Core Global Parameters
Parameter Name	Default Value	Format/Range	Description
NUM_SI	2	Integer (1-16)	Number of Slave Interfaces
NUM_MI	1	Integer (1-64) Range (1-16) when Number of Slave Interfaces > 1, Range (1-64) when Number of Slave Interfaces == 1	Number of Master Interfaces
STRATEGY	0	Integer (0,1,2)	Control the implementation option strategy of the interconnect. If the parameter value is 0, the current settings are used. If the parameter value is 1, features that minimize the area of the infrastructure IP cores used within the interconnect instance are enabled. If the parameter value is 2, features that maximize the performance of the infrastructure IP cores used within the interconnect instance are enabled. (See AXI Interconnect Core — Top Level Settings for details.)

Table 2. AXI Interconnect Core SI-Related Parameters
Parameter Name	Default Value	Format/Range	Description
Snn_HAS_REGSLICE	0	Integer (0, 1, 3, 4)	Controls AXI register slice insertion on SI. If None (0) is selected, no register slice is inserted. If Outer (1) is selected, a register slice is inserted at the SI side of the SI coupler cells hierarchy. If Auto (3) is selected, a register slice is conditionally inserted in the SI coupler cells hierarchy if SI coupler cells with common timing paths are detected. If Outer and Auto (4) is selected, a register slice is inserted at the SI side of the SI coupler cells hierarchy and an additional register slice can be conditionally inserted if SI coupler cells with common timing paths are detected.
Snn_HAS_DATA_FIFO	0	Integer (0, 1, 2)	Insert AXI data FIFO on SI. If parameter value is 0, no data FIFO is inserted. If parameter value is 1, 32-deep data FIFOs are inserted on the W and R channels. If parameter value is 2, 512-deep data FIFOs are inserted on the write and read channels, and their packet mode feature is enabled.

Table 3. Table AXI interconnect Core Advanced Options
Parameter Name	Default Value	Format/Range	Description
ENABLE_ADVANCED_OPTIONS	0	Integer (0,1)	Setting a value of 1 enables a series of advanced configuration parameters (below). Setting a value of 0 disables all advanced configuration parameters.
ENABLE_PROTOCOL_CHECKERS	0	Integer (0,1)	Setting a value of 1 adds an AXI Protocol Checker IP core to each enabled master and slave interface and marks the interfaces for debug.
PCHK_WAITS	0	Integer (0..1024)	Specifies the maximum number of idle cycles for READY monitoring in all of the enabled protocol checkers.
PCHK_MAX_RD_BURSTS	2	Integer (2,4,8,16,32,64)	Specifies the maximum number of outstanding READ transactions per ID in all of the enabled protocol checkers.
PCHK_MAX_WR_BURSTS	2	Integer (2,4,8,16,32,64)	Specifies the maximum number of outstanding WRITE transactions per ID in all of the enabled protocol checkers.
XBAR_DATA_WIDTH	32	Integer (32,64,128,256,512,1024)	If specified, this value overrides any IP integrator automated value for the DATA_WIDTH parameter of the AXI Crossbar within the AXI Interconnect core Instance.
Snn_ARB_PRIORITY	0	Integer (0-15)	Specifies the value for the corresponding Snn_ARB_PRIORITY parameter of the AXI Crossbar instance connecting to the interconnect SI. Available when advanced configuration options are enabled and NUM_SI>1.

Table 4. AXI Interconnect Core MI-Related Parameters
Parameter Name	Default Value	Format/Range	Description
Mnn_HAS_REGSLICE	0	Integer (0, 1, 3, 4)	Controls AXI register slice insertion on MI. If None (0) is selected, no register slice is inserted. If Outer (1) is selected, a register slice is inserted at the MI side of the MI coupler cells hierarchy. If Auto (3) is selected, a register slice is conditionally inserted in the MI coupler cells hierarchy if MI coupler cells with common timing paths are detected. If Outer and Auto (4) is selected, a register slice is inserted at the MI side of the MI coupler cells hierarchy and an additional register slice can be conditionally inserted if MI coupler cells with common timing paths are detected.
Mnn_HAS_DATA_FIFO	0	Integer (0, 1, 2)	Insert AXI Data FIFO on MI If parameter value is 0, no data FIFO is inserted. If parameter value is 1, 32-deep data FIFOs are inserted on the W and R channels. If parameter value is 2, a 512-deep data FIFOs are inserted on the write and read channels, and their packet mode feature is enabled.