•SI data width: 32, 64, 128, 256, 512 or 1,024 bits.
•MI data width: 32, 64, 128, 256, 512 or 1,024 bits (must be different than SI data width).
•When upsizing, data is packed (merged) when permitted by address channel control signals (CACHE modifiable bit is asserted).
•When downsizing, burst transactions are split into multiple transactions if the maximum burst length would otherwise be exceeded.
•When upsizing, the IP core can optionally perform FIFO buffering and clock frequency conversion (synchronous or asynchronous) in a resource-efficient manner.