AXI Data Width Converter - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

°AW and AR channels: One latency cycle.

°W channel when upsizing: One latency cycle (for each cycle in which packing completes), with no bubble cycles on the SI-side (narrow) interface.

°R channel when upsizing: One latency cycle.

°B channel: no latency.

°R channel when downsizing: no latency (for each cycle in which packing completes), with no bubble cycles on the MI-side (narrow) interface.

°W channel when downsizing: no latency.