AXI Data Width Converter Parameters - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)
Document ID
PG059
Release Date
2025-12-19
Version
2.1 English

The following table lists the parameters specific to the AXI Data Width Converter core.

Table 1. AXI Data Width Converter Parameters
Parameter Name Default Value Format/Range Description
SI_DATA_WIDTH 1 32

For AXI4 or AXI3: Integer

(32, 64, 128, 256, 512, 1024); for AXI4-Lite: Integer (32, 64)

Data width of the SI-side Write and

Read datapaths.
MI_DATA_WIDTH 1 64

For AXI4 or AXI3: Integer

(32, 64, 128, 256, 512, 1024); for AXI4-Lite: Integer (32, 64)

 Data width of the MI-side Write and Read datapaths. (Must be different than SI_DATA_WIDTH)
SI_ID_WIDTH 1 0 Integer (0-32) Width of all ID signals (if any) on SI
FIFO_MODE 1 0 Integer (0, 1, 2)
  • 0 = No FIFO
  • 1 = Packet FIFO
  • 2 = Packet FIFO with Clock Conversion

Modes 1 and 2 are supported only when PROTOCOL = AXI3 or AXI4 and SI_DATA_WIDTH < MI_DATA_WIDTH.
ACLK_RATIO 1 1:2 String (“16:1”…”2:1”, “1:2”…"1:16”) Ratio of SI-side clock frequency to MI.
ACLK_ASYN 1 0 Integer (0, 1)

Enable asynchronous conversion.

You can override automatic value from 0 to 1 to force asynchronous conversion. 2

SYNCHRONIZATION_STAGES 2 Integer (2-8) Defines the number of synchronizer stages across the cross clock domain logic.
  1. Automatically set by tools based on system connectivity
  2. Parameter setting is used only when FIFO_MODE = 2.