AXI Data FIFO - 2.1 English - PG059

AXI Interconnect LogiCORE IP Product Guide (PG059)
Document ID
PG059
Release Date
2025-12-19
Version
2.1 English

You can optionally insert AXI Data FIFO cores on selected pathways between the SI, crossbar and MI within the AXI Interconnect core, as needed, to provide data buffering and achieve higher throughput. For each Data FIFO instance, you can selectively enable buffering on the write data channel, read data channel or both.

You can also instantiate the AXI Data FIFO core directly in your design (without AXI Interconnect core) along any pathway between an AXI master and slave device.

Under some circumstances, throughput is improved by buffering data bursts. This is commonly the case when the data rate at an SI or MI differs from the data rate of the AXI Crossbar, typically due to data width or clock rate conversion. Data buffering also allows real-time devices to tolerate transaction arbitration latency. Depending on your interconnect topology, it can be beneficial to place the Data FIFOs before or after the AXI Crossbar, or both.

There are three modes of Data FIFO that can be configured for each of the write and read paths.

  • 32-deep LUT-RAM based FIFO (data channel only).
  • 512-deep block RAM based FIFO (data channel only).
  • 512-deep block RAM based Packet FIFO.

The Packet FIFO mode is used to avoid full/empty stalls in the middle of bursts. In addition to the 512-deep FIFO on the data channel, packet mode also implements a 32-deep FIFO on the corresponding address channel. Enabling packet mode for write causes a delay in the issuing of the write transaction on the AW channel until the entire write data burst (concluded with WLAST) has been received on the SI, thus avoiding stalling due to a slow write data source. Enabling packet mode for read causes a delay in the issuing of the read transaction on the AR channel until the FIFO has enough vacancy to store the entire burst, according to ARLEN . (The “vacancy” is the amount of free space in the R channel FIFO that has not already been committed by previously issued AR commands.) This avoids stalling due to a slow read destination.

Note: Write packet mode does not gate propagation of the write data itself on the MI W-channel of the AXI Data FIFO core. For SI-side packet-mode FIFOs, enabled with AXI Interconnect, the Crossbar does not accept W-channel transfers until after it receives and arbitrates the AW-channel command. For MI-side FIFOs, WVALID can assert on the MI of AXI Interconnect as soon as write data is present. Typically, endpoint slaves do not accept write data until they receive the AW command. However, intervening FIFOs and Register Slices can still propagate write data further downstream without causing any problems for overall transaction processing. Propagating W-transfers before the corresponding AW command is permitted under AXI4 protocol.

AXI Data FIFO does not support buffering of AXI4-Lite transactions.