•Individually configurable for Write and Read datapaths.
•32-deep LUT-RAM based.
•512-deep block RAM based.
•Optional packet FIFO operation to avoid full/empty stalls in the middle of bursts.
•Individually configurable for Write and Read datapaths.
•32-deep LUT-RAM based.
•512-deep block RAM based.
•Optional packet FIFO operation to avoid full/empty stalls in the middle of bursts.