For synchronous conversion, one cycle of the destination interface clock. (For each AXI channel, the destination is the interface in which the VALID signal for that channel is an output.)
For asynchronous conversion, the latency is the same as the FIFO Generator IP for Non-Built-in FIFOs, Independent Clock and first-word fall-through (FWFT). See the FIFO Generator LogiCORE IP Product Guide (PG057) [Ref 3].