| Bits | Description |
|---|---|
| 31:0 | Watchdog Timeout Value A timer in the core resets the transceiver after a certain amount of time has passed with no valid data received. This register holds the number of management clock cycles for the timer to wait before resetting the core. With a management clock speed of 125 MHz, the register times out after around 2s default for 7 series devices. When the register is set to 0x00000000, the watchdog timer is disabled. This is the default condition for UltraScale devices. |