Versal Adaptive SoC Architecture-Based Cores - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The following figure shows the structure of the CPRI IP core output products for Versal adaptive SoC architecture-based cores.

Figure 1. CPRI Core Output Products for Versal Adaptive SoC

The block layer (<component_name>_block.vhd) consists of the following components.

cpri_v8_12.vhd
This is the top-level of the encrypted RTL of the CPRI IP core. The RTL contains the transmit and receive logic, control, and management functions, L1 synchronization logic, and management registers.
<component_name>_versal_gt_and_clocks.vhd
The GT and clocks block contains GT clock buffers, GT reset control, rate change FSMs, GT block sync FSM, 8b10b encoding & decoding, and TX & RX GT quad interfaces.
<component_name>_ori_if.vhd
This file takes the ORI MAC address, port number and, if a slave configuration, the RTWP groups and maps them onto the vendor-specific interface for transmission. In the receive direction the MAC address, port number and, if a master configuration, the RTWP groups are extracted from the vendor-specific data stream and output to the client. See ORI Module for more information.
<component_name>_axi_lite_ipif_wrapper.vhd
When the AXI interface is selected, this file maps between the generic management interface and the AXI4-Lite interface. See Management Interface and AXI4-Lite Memory Mapped Interface for more information.
<component_name>_fc32_rs_fec.v
Optional RS-FEC sub-core for 64b66b line rates only. See RS-FEC Enabled Mode for more information.