Transceiver Status and Control Interface (Versal Adaptive SoC Cores Only) - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)
Document ID
PG056
Release Date
2025-12-03
Version
8.12 English

The following table shows the Versal transceiver status and control ports.

Table 1. Versal Transceiver Status and Control Ports
Port Direction Clock Domain Description
gtpowergood In Async This active-High signal from Versal adaptive SoC. Transceiver indicates when the GT clocking resources have completed power up.
loopback[2:0] Out Management Clock This signal to the Versal adaptive SoC Transceiver controls the various loopback modes.
  1. When the Legacy GT Wizard is selected in the CPRI GUI, the ports gtpowergood and loopback[2:0] are connected between the CPRI core and the Versal adaptive SoC Transceiver using Block Automation, see Block Automation (Versal Adaptive SoC Only) for details.