The following table shows the Versal transceiver status and control ports.
Port | Direction | Clock Domain | Description |
---|---|---|---|
gtpowergood | In | Async | This active-High signal from Versal adaptive SoC. Transceiver indicates when the GT clocking resources have completed power up. |
loopback[2:0] | Out | Management Clock | This signal to the Versal adaptive SoC Transceiver controls the various loopback modes. |
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