Transceiver Loopback and Ethernet Reset Request Register (0x8) - Transceiver Loopback and Ethernet Reset Request Register (0x8) - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2025-12-03
Version
8.12 English
Table 1. Transceiver Loopback and Ethernet Reset Request Register
Bits Description
31:4 Reserved
3:2 Loopback (defaults to 00)

00: Normal Operation

10: Near-end physical medium attachment (PMA) Loopback

01,11: Reserved

1 Reset the Ethernet receive block. Although this bit is writable, it is always read as 0 as the reset is immediate.
0 Reset the Ethernet transmit block. Although this bit is writable, it is always read as 0 as the reset is immediate.