Transceiver Interfaces (Versal Adaptive SoC Cores Only) - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The following table shows the Versal GT TX Interface ports.

Table 1. Versal GT TX IP Interface Ports
Port Direction Clock Domain Description
ch_txdata[127:0] Out System Clock TX data to the Versal adaptive SoC transceiver.
ch_txdiffctrl[4:0] Out Async TX diffctrl to the Versal adaptive SoC transceiver.
ch_txheader[5:0] Out System Clock TX header to the Versal adaptive SoC transceiver.
ch_txinhibit Out System Clock TX inhibit to the Versal adaptive SoC transceiver. Blocks transmission of TX data.
ch_txlatclk Out N/A TX asynchronous gearbox latency clock to the Versal adaptive SoC transceiver. Driven by hires_clk if R21 timers option is selected in CPRI GUI.
ch_txmstdatapathreset 3 Out System Clock TX master data path reset sequence start to the Versal adaptive SoC transceiver.
ch_txmstreset 3 Out System Clock TX master reset sequence start to the Versal adaptive SoC transceiver.
ch_txmstresetdone 3 In System Clock TX master reset sequence done from the Versal adaptive SoC transceiver.
ch_txpmaresetdone 3 In Async TX PMA reset done from the Versal adaptive SoC transceiver.
ch_txpolarity Out System Clock TX polarity control to the Versal adaptive SoC transceiver. Currently not used.
ch_txpostcursor[4:0] Out Async Transmitter post-cursor TX pre-emphasis control to the Versal adaptive SoC transceiver. Currently not used.
ch_txprbssel[3:0] Out System Clock TX PRBS generator test pattern control to the Versal adaptive SoC transceiver. Currently not used.
ch_txprecursor[4:0] Out Async Transmitter pre-cursor TX pre-emphasis control to the Versal adaptive SoC transceiver. Currently not used.
ch_txrate[7:0] Out System Clock TX line rate control to the Versal adaptive SoC transceiver.
ch_txsequence[6:0] Out System Clock TX sequence counter to the Versal adaptive SoC transceiver.
ch_txuserrdy 3 Out System Clock TX user clocks stable to the Versal adaptive SoC transceiver.
  1. CPRI only uses the above subset of the available signals on the Versal adaptive SoC Transceiver Tx_GT_IP_Interface. For further details, see the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
  2. The ports in the preceding table are connected between the CPRI core and the Versal adaptive SoC Transceiver using Block Automation when the Legacy GT Wizard is selected in the CPRI GUI.see Block Automation (Versal Adaptive SoC Only) for details. When the GT Wizard Subsystem is selected in the CPRI GUI, no Block Automaton is available. The GT TX Interface should be connected manually to the GT Wizard Subsystem.
  3. These ports are only present when the Legacy GT Wizard is selected in the CPRI GUI.

The following table shows the Versal GT RX Interface ports.

Table 2. Versal GT RX IP Interface Ports
Port Direction Clock Domain Description
ch_rxdata[127:0] In Recovered Clock RX data from the Versal adaptive SoC transceiver.
ch_rxdatavalid[1:0] In Recovered Clock RX data valid from the Versal adaptive SoC transceiver.
ch_rxgearboxslip Out Recovered Clock RX Gearbox Slip to the Versal adaptive SoC transceiver.
ch_rxheader[5:0] In Recovered Clock RX Header from the Versal adaptive SoC transceiver.
ch_rxheadervalid[1:0] In Recovered Clock RX Header Valid from the Versal adaptive SoC transceiver.
ch_rxlatclk Out N/A RX asynchronous gearbox latency clock to the Versal adaptive SoC transceiver. Driven by hires_clk if R21 timers option is selected in CPRI GUI.
ch_rxlpmen Out Async RX LPM mode enable to the Versal adaptive SoC transceiver.
ch_rxmstdatapathreset 3 Out Recovered Clock RX master data path reset sequence start to the Versal adaptive SoC transceiver.
ch_rxmstreset 3 Out Recovered Clock RX master reset sequence start to the Versal adaptive SoC transceiver.
ch_rxmstresetdone 3 In Recovered Clock RX master reset sequence done from the Versal adaptive SoC transceiver.
ch_rxpmaresetdone 3 In Async RX PMA reset done from the Versal adaptive SoC transceiver.
ch_rxpolarity Out Recovered Clock RX polarity control to the Versal adaptive SoC transceiver. Currently not used.
ch_rxprbscntreset Out Recovered Clock RX PRBS error count reset to the Versal adaptive SoC transceiver.
ch_rxprbssel[3:0] Out Recovered Clock RX PRBS generator test pattern control to the Versal adaptive SoC transceiver. Currently not used.
ch_rxrate[7:0] Out Recovered Clock RX line rate control to the Versal adaptive SoC transceiver.
ch_rxuserrdy 3 Out Recovered Clock RX user clocks stable to the Versal adaptive SoC transceiver.
  1. CPRI only uses the above subset of the available signals on the Versal adaptive SoC Transceiver Rx_GT_IP_Interface. For further details the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
  2. The ports in the preceding table are connected between the CPRI core and the Versal adaptive SoC Transceiver using Block Automation, when the Legacy GT Wizard is selected in the CPRI GUI. see Block Automation (Versal Adaptive SoC Only) for details. When the GT Wizard Subsystem is selected in the CPRI GUI, no Block Automaton is available. The GT RX Interface should be connected manually to the GT Wizard Subsystem.
  3. These ports are only present when the Legacy GT Wizard is selected in the CPRI GUI.