Ports Added in Version 8.0 - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)
Document ID
PG056
Release Date
2025-12-03
Version
8.12 English

The ports in the following three tables were added to version 8.0 of the core.

Table 1. Quad PLL Clock Ports
Port Direction Upgrade Action
Virtex 7, Kintex 7, and Zynq 7000 SoC Implementations
qpllclk_out Out Leave open
qpllrefclk_out Out Leave open
qplllock_out Out Leave open
Artix 7 Implementations
pll0clk_out Out Leave open
pll0refclk_out Out Leave open
pll1clk_out Out Leave open
pll1refclk_out Out Leave open
Table 2. Alignment Interface
Port Direction Upgrade Action
phase_alignment_done_out Out Leave open
txdlysreset_out[2:0] Out Tie to txdlysresetdone_in[2:0]
txdlysresetdone_in[2:0] In Tie to txdlysreset_out[2:0]
txphinit_out[2:0] Out Tie to txphinitdone_in[2:0]
txphinitdone_in[2:0] In Tie to txphinit_out[2:0]
txphalign_out[2:0] Out Tie to txphaligndone_in[2:0]
txphaligndone_in[2:0] In Tie to txphalign_out[2:0]
txdlyen_out[2:0] Out Leave open
Table 3. Transceiver Debug Interface(1)
Port Direction Upgrade Action
gt0_eyescantrigger_in In Tie Low
gt0_eyescanreset_in In Tie Low
gt0_eyescandataerror_out Out Leave open
gt0_txdiffctrl_in In Tie to 1010
gt0_txpostcursor_in In Tie to 00000
gt0_txprecursor_in In Tie to 00000
gt0_txpolarity_in In Tie Low
gt0_rxpolarity_in In Tie Low
gt0_rxdfelpmreset_in In (GTXE2 and GTHE2-based cores only) Tie Low
gt0_rxlpmen_in In (GTXE2 and GTHE2-based cores only) Tie Low
gt0_rxlpmreset_in In (GTPE2-based cores only) Tie Low
gt0_rxlpmhfhold_in In (GTPE2-based cores only) Tie Low
gt0_rxlpmhfovrden_in In (GTPE2-based cores only) Tie Low
gt0_rxlpmlfhold_in In (GTPE2-based cores only) Tie Low
gt0_rxdisperr_out Out Leave open
gt0_rxnotintable_out Out Leave open
gt0_rxresetdone_out Out Leave open
gt0_txresetdone_out Out Leave open
  1. Ports only present when the Additional Transceiver Control and Status Ports option is selected.