Port Changes in Version 8.12 - Port Changes in Version 8.12 - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2025-12-03
Version
8.12 English

The following ports were added in version 8.12 (2024.2) of the core in Versal Adaptive SoC cores, using the new GT Wizard subsystem only.

Table 1. Ports added in Version 8.12 (2024.2)
Port Direction Upgrade Action
reset_all Out Connect to GT Wizard subsystem port of same name.
reset_tx_pll_and_datapath Out Connect to GT Wizard subsystem port of same name.
reset_tx_datapath Out Connect to GT Wizard subsystem port of same name.
reset_rx_pll_and_datapath Out Connect to GT Wizard subsystem port of same name.
reset_rx_datapath Out Connect to GT Wizard subsystem port of same name.
reset_tx_done In Connect to GT Wizard subsystem port of same name.
reset_rx_done In Connect to GT Wizard subsystem port of same name.
tx_bufg_gt_clr In Connect to GT Wizard subsystem port of same name.
rx_bufg_gt_clr In Connect to GT Wizard subsystem port of same name.

The following ports were removed in version 8.12 (2024.2) of the core in Versal Adaptive SoC cores.

Table 2. Ports removed in Version 8.12 (2024.2)
Port Direction Upgrade Action
ch_txctrl0 Out N/A
ch_txctrl1 Out N/A
ch_txctrl2 Out N/A
ch_txphdlypd Out N/A
ch_txphdlyreset Out N/A
ch_txphdlyresetdone In N/A
ch_txsyncallin Out N/A
ch_txsyncdone In N/A
ch_rxctrl0 In N/A
ch_rxctrl1 In N/A
ch_rxctrl2 In N/A
ch_rxctrl3 In N/A
ch_rxphdlypd Out N/A
ch_rxphdlyreset Out N/A
ch_rxphdlyresetdone In N/A
ch_rxresetdone In N/A
ch_rxsyncallin Out N/A
ch_rxsyncdone In N/A
encommaalign Out N/A