The bits in this register define the line speeds that the core should use.
| Bits | Description |
|---|---|
| 31:15 | Reserved |
| 14 | Capable of 24,330.24 Mb/s FEC Enabled Mode (Versal GTY/GTYP or UltraScale GTYE3/GTYE4 only) |
| 13 | Capable of 12,165.12 Mb/s FEC Enabled Mode (Versal GTY/GTYP or UltraScale GTYE3/GTYE4 only) |
| 12 | Capable of 10,137.6 Mb/s FEC Enabled Mode (Versal GTY/GTYP or UltraScale GTYE3/GTYE4 only) |
| 11 | Capable of 8,110.08 Mb/s FEC Enabled Mode (Versal GTY/GTYP or UltraScale GTYE3/GTYE4 only) |
| 10 | Capable of 24,330.24 Mb/s (Versal GTY/GTYP or UltraScale GTYE3/GTYE4 only) |
| 9 | Capable of 12,165.12 Mb/s |
| 8 | Capable of 8,110.08 Mb/s |
| 7 | Capable of 10,137.6 Mb/s |
| 6 | Capable of 9,830.4 Mb/s |
| 5 | Capable of 6,144.0 Mb/s |
| 4 | Capable of 4,915.2 Mb/s |
| 3 | Capable of 3,072.0 Mb/s |
| 2 | Capable of 2,457.6 Mb/s |
| 1 | Capable of 1,228.8 Mb/s (Not available Versal GTY/GTYP) |
| 0 | Capable of 614.4 Mb/s (Not available Versal GTY/GTYP) |
|
|
The following table shows the default values for the Line Speed Capability Register, depending on the speed capability that is selected.
| Core Speed Capability | Line Speed Capability Register (0xD) Default Values |
|---|---|
| 24,330.24 Mb/s | 368.64 MHz reference clock: 000 0111 0000 0000 245.76 MHz reference clock: 000 0111 1111 1111 |
| 24,330.24 Mb/s with FEC | 368.64 MHz reference clock: 111 1111 0000 0000 245.76 MHz reference clock: 111 1111 1111 1111 |
| 12,165.12 Mb/s | 368.64 MHz reference clock: 000 0011 0000 0000 307.20 and 245.76 MHz reference clock: 000 0011 1111 1111 |
| 10,137.6 Mb/s | 000 0000 1111 1111 |
| 9,830.4 Mb/s | 000 0000 0111 1111 |
| 6,144.0 Mb/s | 000 0000 0011 1111 |
| 4,915.2 Mb/s | 000 0000 0001 1111 |
| 3,072.0 Mb/s | 000 0000 0000 1111 |