| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family(1) |
AMD Versal™
Adaptive SoC
6
AMD Zynq™ UltraScale+™ MPSoC, RFSoC UltraScale+ FPGA(5) UltraScale FPGA AMD Zynq™ 7000 SoC (2) 7 series FPGA(3) See Speed Grade Support. |
| Supported User Interfaces | Generic data, status, configuration, and management interfaces, AXI4-Lite management interface |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Encrypted register transfer level (RTL) |
| Example Design | VHDL |
| Test Bench | VHDL |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | VHDL, Verilog |
| Supported S/W Driver | N/A |
| Tested Design Flows(4) | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54473 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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