Hard FEC Wrapper IP Cores - Hard FEC Wrapper IP Cores - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)
Document ID
PG056
Release Date
2025-12-03
Version
8.12 English
UltraScale+ architecture
For standalone Hard FEC wrapper IP cores the delay through the Hard FEC wrapper is 26 datapath clock cycles plus the variable delay caused by the Hard FEC alignment process. This is between 150 and 230 datapath clock cycles.
Table 1. Hard FEC Wrapper IP Core Delay (Cycles)
Minimum Latency (cycle) Maximum Latency (cycles)
26+150 = 176 26+230 = 256

The CDC FIFO is instantiated in Hard FEC wrapper IP cores and must also be included in any latency calculation. See section Delay Across the CDC FIFO for details.

The delay through the transceiver must also be include in any latency calculation. See section Delay Measurement and Requirement 21 (R21) for details.