This is only applicable to selected UltraScale+ devices. Refer to UltraScale Architecture and Product Data Sheet: Overview (DS890) for details.
When the Generate a Hard FEC CPRI wrapper option is selected, the CPRI IP core is converted into a 4 lane Hard RS-FEC Receiver IP core.
The following table lists the ports where chx refers to CPRI channels 0, 1, 2, or 3.
Important: The Hard FEC sub-core
(CMAC) must be placed in the same SLR of the device as the GTYE4 transceiver to guarantee
timing closure. See
UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) and
Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075) for details. See Constraining the Core.
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| rx_fast_clk | In | N/A | Hard FEC wrapper clock 368.64 MHz, used on the 66bit ingress and egress datapaths. |
| rx_fast_reset | In | rx_fast_clk | Hard FEC wrapper reset. Active-High input. |
| hires_clk | In | N/A | High resolution sampling clock used to measure the transit time of the clock domain crossing FIFOs. Must be at least 380 MHz. |
| rsfec_clk | In | N/A |
RS-FEC clock input:
|
| all_clk_locked | In | N/A | Assert High when rx_fast_clk, rsfec_clk, and hires_clk input clocks are all stable. |
| rsfec_enable_correction | In | rx_fast_clk | When set High, enables FEC correction. |
| rsfec_enable_indication | In | rx_fast_clk | When set High, enables FEC indication of total CWs and corrected and uncorrected CWs. |
| rx_rsfec_enable_chx | In | rx_rec_clk_chx | Hard FEC wrapper channel enable input from CPRI lanes 0-3. Drive high to enable each CPRI channel through the RS-FEC. |
| rx_rec_clk_chx | In | N/A | Recovered clock from CPRI lanes 0-3. |
| rx_serdes_data_chx(63:0) | In | rx_rec_clk_chx | 64-bit data from CPRI lanes 0-3. |
| rx_serdes_head_chx(1:0) | In | rx_rec_clk_chx | 2-bit header from CPRI lanes 0-3. |
| rx_gbx_slip_chx | Out | rx_rec_clk_chx | Receive gearbox slip output to GTs in CPRI lanes 0-3. Slips the GT gearbox contents when pulsed high. |
| cdc_reset_chx | In | rx_fast_clk | Hold CDC FIFO in reset until clocks are stable. |
| fifo_fill_level_chx(8:0) | In | Management Clock | In master cores the starting level of the CDC FIFO can be set using this input port. By default the CDC FIFO fills to fill_level=64 before reading is enabled. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced. |
| average_chx(16:0) | Out | hires_clk | Averaged CDC FIFO transit time value. This value can be converted to UI by multiplying by 66 and dividing by 256. |
| average_rdy_chx | Out | hires_clk | Averaged CDC FIFO transit time value ready.Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 0-3.(3) |
| average_ack_chx | In | Management Clock | Averaged CDC FIFO transit time value acknowledge. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 0-3.(3) |
| fifo_error_chx | Out | rx_fast_clk | Indicates a FIFO full or FIFO empty condition. This cause cdc_reset to assert. |
| cdc_rxdata_chx(63:0) | Out | rx_fast_clk | 64-bit data from Hard FEC wrapper to CPRI lanes 0-3. This is the data from the read port of the CDC FIFO is intended to be used by the receiving CPRI core for non-FEC line rates. |
| cdc_rxheader_chx(1:0) | Out | rx_fast_clk | 2-bit header from Hard FEC wrapper to CPRI lanes 0-3. This is the header from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates. |
| pcs_rxdata_chx(63:0) | Out | rx_fast_clk | 64-bit data from Hard FEC wrapper to CPRI lanes 0-3. |
| pcs_rxheader_chx(1:0) | Out | rx_fast_clk | 2-bit header from Hard FEC wrapper to CPRI lanes 0-3. |
| pcs_rxheadervalid_chx | Out | rx_fast_clk | This output indicates the start of a codeword on CPRI lanes 0-3. |
| stat_rx_aligned_status_chx | Out | rx_fast_clk | When High this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data. |
| stat_cw_inc_chx | Out | rx_fast_clk | Active-High pulse Indicates a received RS-FEC codeword. |
| stat_corrected_cw_inc_chx | Out | rx_fast_clk | Active-High pulse Indicates a corrected RS-FEC codeword. |
| stat_uncorrected_cw_inc_chx | Out | rx_fast_clk | Active-High pulse Indicates an uncorrected RS-FEC codeword. |
| hfec_fifo_latency_chx(15:0) | Out | rx_fast_clk | Variable latency through the Hard FEC Wrapper to CPRI channels 0-3. This value can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. The value is the number of rx_fast_clk clock cycles. Multiply by 66 to get the latency in UI. |
| hfec_fifo_latency_rdy_chx | Out | rx_fast_clk | Hard FEC FIFO Latency ready signal. Handshake signal used for clock domain crossing the latency value from the Hard FEC wrapper to the external CPRI cores 0-3. Signal is high when the latency value is ready to be transferred. |
| hfec_fifo_latency_ack_chx | In |
Management Clock Channel (0-3) |
Hard FEC FIFO Latency acknowledge signal. Handshake signal used for clock domain crossing the latency value from the Hard FEC wrapper to the external CPRI cores 0-3. If it is not necessary to perform clock crossing on hfec_fifo_latency_chx, these ports should be permanently driven High. Otherwise wait until ready signal is high and then pulse acknowledge High when the latency value has been transferred. |
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