When using RS-FEC enabled cores, this register allows the user to inject bit errors into the FEC in order to test its operation. One bit within a 64-bit word is inverted and an LFSR randomizes the position of the inverted bit. There are five preset BERs as shown in the following table. Most BERs result in the FEC reporting corrected codewords in register 0x1D. The largest BER has too many errors for the FEC to correct, and it reports uncorrected codewords in register 0x1E. Three consecutive uncorrected codewords cause the RS-FEC to fall out of alignment, after which point it attempts to realign. A lower BER must be selected to allow the FEC to regain alignment.
| Bits | Description |
|---|---|
| 31:10 | Reserved |
| 9:4 | FEC error inject seed LFSR seed for randomizing the position of the corrupted bit within the 64-bit word. |
| 3:0 | FEC error inject Select bit error injection rate: b'0001': 1:16 codewords (~12 ppm) b'0010': 1:8 codewords (~25 ppm) b'0100': 1:4 codewords (~50 ppm) b'1000': 1:2 codewords (~100 ppm) b'1111': 1:1 64-bit word (~15625 ppm) Any other binary value does not inject bit errors into the RS-FEC. |
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