Delay Through the Versal Adaptive SoC GTYP Transceiver - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

Delay through the Versal GTYP transceiver consists of a variable component (barrel shift or TX and RX gearbox latency) and a fixed component. The fixed component is made up of the delay shown in the following table plus the additional line rate delay shown below.

Table 1. Fixed Contribution to Delay - Versal Adaptive SoC GTYP Transceiver
Block Latency (UI)
TX 32-bit datapath cores (8b/10b) 156
64-bit datapath cores (64b/66b) 276
RX 32-bit datapath cores (8b/10b) 242
64-bit datapath cores (64b/66b) 340