Delay through the Versal GTY transceiver consists of a variable component (barrel shift or TX and RX gearbox latency) and a fixed component. The fixed component is made up of the delay shown in the following table plus the additional line rate delay shown below.
Block | Latency (UI) | |
---|---|---|
TX | 32-bit datapath cores (8b/10b) | 156 |
64-bit datapath cores (64b/66b) | 276 | |
RX | 32-bit datapath cores (8b/10b) | 242 |
64-bit datapath cores (64b/66b) | 340 |