Delay Model - Delay Model - 8.12 English - PG056

The following figure shows the delay model used for the CPRI core in a master configuration. As illustrated, there are contributions to the end-to-end delay from the FPGA logic portion of the core, the clock domain crossing FIFO in the receive path, the transceiver, and the cable itself. In cores supporting 10,137.6 Mb/s or 12,165.12 Mb/s on 7 series devices, a clock domain crossing FIFO is also present in the transmit path. Cable delay can be inferred from the R21 coarse timer measurement, the FIFO transit time measurement and the transceiver delay, through the use of the T₁₄ delay value shown in the following figure. The slave configuration is similar but the T₁₄ value becomes T_offset, as shown in the next to the following figure.

Figure 1. Delay Model for the CPRI Core - Master Configuration

Figure 2. Delay Model for the CPRI Core - Slave Configuration

The next sections expand upon each of the contributions to the delay model and demonstrate how to determine the cable delay (CPRI Requirement 21) from the R21 coarse timer measurement, the FIFO transit time measurement, and the transceiver delay.

7 Series and Ultrascale

In UltraScale and 7 series-based cores with 8b10b line rates, the variable component is represented by the position of the RX comma alignment barrel shifter. This value, measured in UI, is continually monitored by the core and is presented through the management interface, address 0x9 and on the barrel_shift_value[6:0] output port in the control and status interface. For 64b66b line rates on 7 series-based cores, the barrel shift value should be ignored.

In UltraScale architecture-based cores using 64b66b line rates, the transceiver is used in asynchronous gearbox mode. In this mode the variable component is represented by the delay across the transmit and receive gearboxes, tx_gb_latency, and rx_gb_latency. These values, measured in 1/8 UI, are continually monitored by the core and presented through the management interface, address 0x16 and on the tx_gb_latency_value [15:0] and rx_gb_latency_value [15:0] output ports in the control and status interface. For 8b10b line rates on UltraScale architecture-based cores, the barrel shift value should be used instead of the TX and RX gearbox latencies.

In UltraScale architecture-based cores running at 64b66b line rates, the delay across the transmit gearbox effectively replaces the delay across the transmit CDC FIFO present in 7 series-based cores.

In UltraScale architecture-based cores running at 64b66b line rates, the delay across the receive gearbox effectively replaces the delay across the RX comma alignment barrel shifter present in 8b10b line rates.

Versal Adaptive SoC

In Versal adaptive SoC cores using 64b66b line rates, the transceiver is used in asynchronous gearbox mode. In this mode, the variable component is represented by the delay across the transmit and receive gearboxes, tx_gb_latency, and rx_gb_latency. These values measured in 1/8 UI must be read from the Versal GT Quad or GT Wizard subsystem through an AXI or APB interface. When reading the gearbox latency registers through an AXI interface 3 66-bit clock cycles of latency (198UI) should be added to the combined value. For full details see the sections on TX & RX Asynchronous Gearbox Reading the Datapth Latency in Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).

In Versal adaptive SoC cores using 8b10b line rates, the RX comma alignment barrel shift value should be used instead of the TX and RX gearbox latencies. The RX comma alignment barrel shift value, measured in UI, is continually monitored by the core and is presented through the management interface, address 0x9 and on the barrel_shift_value[6:0] output port in the control and status interface.