- UltraScale+ architecture
- For Hard FEC enabled cores running a non-FEC linerate, the additional
delay through the core is 14 datapath clock cycles. This equates to 924 UI with a 64-bit
datapath. For cores running with a FEC Enabled line rate, the additional delay through
the core is 13 datapath clock cycles, which equates to 858 UI with a 64-bit datapath.
The additional delay added by the FECs is 44 datapath clock cycles (TX: Soft FEC 18 and RX: Hard FEC 26) and equates to 2904 UI with a 64-bit datapath, plus the variable component of the Hard FEC latency, which is added by the Hard FEC alignment process. This is between 150 and 230 datapath clock cycles. See Hard FEC Variable Latency Register (0x20) for details.
| Line Rate Mode | Minimum Latency (cycle) | Maximum Latency (cycles) |
|---|---|---|
| Non FEC line Rate | 14 | 14 |
| FEC Line Rate | 13+44+150 = 207 | 13+44+230 = 287 |