Cores Supporting 3,072.0 Mb/s - Cores Supporting 3,072.0 Mb/s - 8.12 English - PG056

UltraScale architecture, Zynq 7000 SoC, Virtex 7, and Kintex 7 devices

The additional delay through the core is five datapath clock cycles, or 100 UI.

Artix 7 devices

The additional delay through the core is five datapath clock cycles plus two RECCLK cycles, or 240 UI.