Cores Supporting 12,165.12 Mb/s and Above - 8.12 English - PG056

UltraScale architecture

The additional delay is 12 datapath clock cycles when operating at 8,110.08, 10,137.6, 12,165.12, or 24,330.24 Mb/s and 10 datapath clock cycles otherwise. 12 datapath clock cycles equates to 396 UI when the core is operating with a 32-bit datapath and 792 UI with a 64-bit datapath. At 8b10b line rates, 10 datapath clock cycles equates to 400 UI when the core is operating with a 32-bit datapath, and 800 UI with a 64-bit datapath.

Versal Adaptive SoC

The additional delay is 11 datapath clock cycles when operating at 64b66b line rates, which equates to 726UI with a 64-bit datapath. At 8b10b line rates the additional delay is 840UI, which equates to 5 Tx cycles at 80-bit datapath plus 11 Rx cycles at 40-bit datapath.