The ports in the following table were re-named or re-sized in version 8.0 of the CPRI core. Their functionality remains the same.
| Port Description | Version 7.0 | Version 8.0 |
|---|---|---|
| System clock output | core_clk | clk_out |
| System clock OK | clk_ok | clk_ok_out |
| AXI Write Address | s_axi_awaddr[31:0] | s_axi_awaddr[11:0] |
| AXI Read Address | s_axi_araddr[31:0] | s_axi_araddr[11:0] |