VSEC Capability Register 2 (Offset 0x200) - 2.9 English

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9 LogiCORE IP Product Guide (PG055)

Document ID
PG055
Release Date
2023-11-24
Version
2.9 English

The VSEC capability register (described in Table: VSEC Capability Register 2 ) allows the memory space for the core to appear as though it is a part of the underlying integrated block PCIe configuration space. The VSEC is inserted immediately following the last enhanced capability structure in the underlying block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19 of v2.0) [Ref 8] .

This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.

Table 2-20: VSEC Capability Register 2

Bits

Name

Core Access

Reset
Value

Description

15:0

VSEC Capability ID

RO

0x000B

PCI-SIG defined ID identifying this Enhanced Capability as a Vendor-Specific capability. Hardcoded to 0x000B.

19:16

Capability Version

RO

0x1

Version of this capability structure. Hardcoded to 0x1.

31:20

Next Capability Offset

RO

0x000

Offset to next capability.