|
Port
|
Direction
|
Width
|
Description
|
|
pipe_txprbssel
|
I
|
3
|
PRBS input.
|
|
pipe_rxprbssel
|
I
|
3
|
PRBS input.
|
|
pipe_rxprbsforceerr
|
I
|
1
|
PRBS input.
|
|
pipe_rxprbscntrreset
|
I
|
1
|
PRBS input.
|
|
pipe_loopback
|
I
|
1
|
PIPE loopback.
|
|
pipe_rxprbserr
|
O
|
1
|
PRBS output.
|
|
pipe_rst_fsm
|
O
|
|
Should be examined if
pipe_rst_idle
is stuck at 0.
|
|
pipe_qrst_fsm
|
O
|
|
Should be examined if
pipe_rst_idle
is stuck at 0.
|
|
pipe_sync_fsm_tx
|
O
|
|
Should be examined if
pipe_rst_fsm
stuck at 11'b10000000000, or
pipe_rate_fsm
stuck at 24'b000100000000000000000000.
|
|
pipe_sync_fsm_rx
|
O
|
|
Deprecated.
|
|
pipe_drp_fsm
|
O
|
|
Should be examined if
pipe_rate_fsm
is stuck at 100000000.
|
|
pipe_rst_idle
|
O
|
|
Wrapper is in IDLE state if
pipe_rst_idle
is High.
|
|
pipe_qrst_idle
|
O
|
|
Wrapper is in IDLE state if
pipe_qrst_idle
is High.
|
|
pipe_rate_idle
|
O
|
|
Wrapper is in IDLE state if
pipe_rate_idle
is High.
|
|
PIPE_DEBUG_0/gt_txresetdone
|
O
|
|
Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_1/gt_rxresetdone
|
O
|
|
Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals.The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_2/gt_phystatus
|
O
|
|
Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_3/gt_rxvalid
|
O
|
|
Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_4/gt_txphaligndone
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_5/gt_rxphaligndone
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_6/gt_rxcommadet
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_7/gt_rdy
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_8/user_rx_converge
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
PIPE_DEBUG_9/PIPE_TXELECIDLE
|
O
|
|
Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUG_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
|
|
pipe_txinhibit
|
I
|
1
|
Connects to TXINHIBIT on transceiver channel primitives.
|